1. Field of Invention
The present invention relates to integrated circuit packaging and in particular to high performance packaging of integrated circuit chips in a three dimensional package.
2. Description of Related Art
Conventional packaging of integrated circuit chips is in individual packages which are in turn mounted in a planar fashion on a printed circuit board. Often the printed circuit board is in the form of a card which is plugged into a mother board which has other cards mounted in a vertical orientation stemming from an edge connector on the card. To communicate between chips a signal is passed through the signal I/O of the chip, then the signal I/O of the module on which the chip is mounted, through the wiring of a card if one exists, across the wiring of the mother board and back through another card, through the another module and onto another chip. Each time there is a package change, there is some form of a connector which limits the bandwidth and frequency at which the chip to chip communications can be performed. The printed circuit wiring of the modules, cards and board produces delays including perturbations caused by parasitic impedance that limits performance. These delays and perturbations limit the performance of the signals outside the semiconductor chips and in turn limit the performance of the system in which the chips operate.
In U.S. Pat. No. 5,838,060 (Comer) a stacked printed circuit package is shown in which each printed circuit card in the package contains one integrated circuit chip connected to a set of peripherally located I/O terminals. The configuration allows a very tight stacking of printed circuit cards both in a vertical and a horizontal direction. In U.S. Pat. No. 5,777,345 (Loder et al.) an electronic package has a plurality of physically stacked integrated circuit die. Within the package a first die is mounted with leads connected to bond pads. Then a second die is physically mounted on top of the first die and electronically connected to the first die by connecting its leads to the bond pads of the package. In U.S. Pat. No. 5,737,192 (Linderman) a stack of chips are vertically mounted in a well etched in a substrate with a patterned overlay to provide signal connections to each of the stacked chips. In U.S. Pat. No. 5,682,062 (Gaul) shows a stacked set of semiconductor dies with interconnections formed from etched holes filled with a metal starting at the front and extending to the back side of the die. Conductive material in the form of prongs extending from the etched holes of a first die are used to mate with holes of a second die that receive the prongs and form a conductive path from the first die to the second die. In U.S. Pat. No. 5,432,999 (Capps et al.) a process is described for forming a stackable integrated circuit die that can be stacked with other similar die. The integrated circuit die is formed by first forming the posts that are the conductive vias which go through the die and then forming the semiconductor material around posts upon which the integrated circuit is created. In U.S. Pat. No. 5,347,428 (Carson et al.) either a vertical or a horizontal stack of memory chip mounted on a processor chip is described. The signal from the stack of chips is brought out to the edge of each memory chip from where they can be connected to bond pads and then to the processor chip.
An electronic package performs four primary functions: hold, interconnect, power and cool the semiconductor chips that the package was designed to accommodate. Conventional packaging today performs these four basic functions, but at the limitation of performance because the chips are physically and electrically separated by several different package levels and long signal wires. The electrical discontinuities at the transition from one package level to another adds delay caused by parasitic impedance of the package interfaces to an already long wiring delay. At the speed of today""s chips this delay external to the semiconductor chips limits the packaged performance below that which could otherwise be attained if everything could be contained within semiconductor chips or within short distances and having a minimum number of package boundaries for signals to traverse.
A three dimensional package, containing a stack of semiconductor chips on an external interface substrate with wiring between chips going through the stack of chips in such a way as to form chip to chip vias, produces a package that has the opportunity to minimize the delay between chips. If the chip to chip vias can be limited to just those chips that need to communicate by forming interstitial chip to chip vias, then the particular column location of the chip to chip via can be used for more than one chip interconnect and the parasitic impedance of the interconnect can be held to a minimum. This can enhance both wireability and performance between chips. In addition to providing tight physical packaging of semiconductor chips, a three dimensional package need to accommodate a means of cooling the package. If a cooling capability can be integrated into the tight stacking of chips, then a complete package can be produce to support numerous high performance needs.
In the present invention a three dimensional package is described in which semiconductor chips are stacked front to back and to an I/O interface substrate in a pancake like configuration. The I/O interface substrate sits at the bottom of the stack and provides for power and signal connections from external to the stack of chips through a pin array on the side opposite to where connections are made to the chip stack. An array of columns of chip to chip (CTC) vias is created going through each semiconductor chip in the stack to carry power and signal from the I/O interface substrate to the chips in the stack. Signal communications between chips in the stack also use the CTC vias. Segments of the CTC vias within each chip are capped with solder bumps on both the top and bottom sides of each chip. The I/O substrate has an array of solder bumps which are connected to the array of I/O pins and that match the array on the back side of the bottom chip in the stack of chips. The solder bumps on the chip stack and the I/O substrate are aligned, and the stack and substrate are clamped together and heated to reflow the solder bumps. This makes both a physical and an electrical connection between the chips in the stack and the I/O interface substrate.
A segment of the array of CTC vias is formed in each chip by etching holes into the back side of the semiconductor chips until the field oxide layer under the first level of metalization is reached. Then the holes are etched through the field oxide to a metal land in the first level of metal on the top side of the chip. An oxide insulating layer is formed on the walls of the holes, and each hole is filled with a metal and capped with an solder bump. Holes on the top side of the chip located over the holes on the backside are opened in the inter metal dielectric. These holes on the top side are opened to the second level of metal inside the chip and are capped with a solder bump. An interlevel via between the first and second levels of metalization within the chip completes the CTC via segment and provides electrical continuity between the solder bumps on the back of the chip and the solder bumps on the front side of the chip.
The interlevel via between first and second levels of metalization within the chip plays an important role in the forming of the array of CTC vias. When the interlevel via is connected between the first and second levels of metalization, the CTC via is continuous through the chip and signals appearing at a solder bump on the back side of a chip also appear at a solder bump on the top side of a chip. When the interlevel via is not present, the CTC via is open allowing the column in which the open CTC exists to have interstitial connections where the column can support signals of more than one function at the same time. When a CTC vias is open, a signal for one function can enter the chip through a first part of the open CTC via and a second signal for a different function can be sent from the chip through the second part of the open CTC. Thus formed, the interstitial CTC vias can allow different functions to use the same column location, reducing the need for more CTC via holes on the stacked chips and enhancing the wireability between the stack of chips. Using the wiring levels internal to the stacked chip and the ability to open a CTC via stack by leaving out the interlevel via, different interstitial vias in different CTC via stacks can be electrically connected to further enhance wireability between chips in the stack. The internal wiring of the stacked chips can tie together multiple CTC via stacks as might be desired when distributing power, or the internal wiring in conjunction with the interlevel vias might be used to broadcast a signal to multiple CTC via stacks or to multiple interstitial vias such as might be desired with a clock signal.
To accommodate cooling each chip in the stack is made of different size. Starting with the bottom chip and progressing to the top chip, each successive chip is made smaller than the chip directly below it, but larger than the active area of the chip including the CTC via area. When the chips are stacked together they look like steps in a stair case when viewed edge on. The size differences in the chips and the location of the active area within the chips can create a stepped arrangement on any combinations of the four sides of the chips including all four sides. Solder bumps are deposited on each chip in the area of the steps of the xe2x80x9cstair casexe2x80x9d which extending out beyond the chip mounted above it. One or more heat sinks are attached to the stack of chips by means of the soldering the heat sinks to the solder bumps in the stepped area. Depending on the cooling requirements, one or more heat sinks can be attached to the steps of the chips. If no heat sinking capability is required, the chips in a stack can all be the same size with no stair case like configuration.